The present invention relates to integrated circuits. More particularly, the present invention relates to a power ring architecture for integrated circuits.
An integrated circuit (IC), and, in particular, a system on chip (SoC), may be powered by a plurality of power supplies, each power supply providing power to a different section or component of the IC. As shown in FIG. 1, a semiconductor chip 10 includes a first bond pad 12, a second bond pad 14, and a third bond pad 16. Each of bond pads 12, 14, and 16 represents a power supply point for its respective circuitry (not shown) on chip 10. Chip 10 is powered via an external high voltage power line 18. Between power line 18 and each of bond pads 12, 14, and 16, is a first low drop off regulator (LDO) 20, a second LDO 22, and a third LDO 24, respectively.
Each of LDOs 20, 22, and 24 is also external to chip 10, and is configured to step down the high voltage from power line 18 to an operating power-supply voltage for the circuitry included in chip 10. More than one LDO is utilized because the voltage requirement for the circuitry associated with each of bond pads 12, 14, and 16 may be different from one another. For example, the circuitry associated with first bond pad 12 may be a digital circuit and have a lower operating voltage than an analog circuit associated with second bond pad 14.
External LDOs, however, occupy valuable space on a circuit board and/or produce design or assembly challenges relating to alignment, die size, or wire layout restrictions. Such design or assembly challenges also increase the overall system cost.
Thus, there is a need for an IC layout that provides embedded or internal LDOs. There is a further need for an IC having embedded LDOs with minimal change to its internal circuitry. There is still a further need for an IC architecture that provides flexibility in the position and number of internal power supply points.